A 7th Framework Programme Collaborative Project funded by the European Union
APACHE Technical Objectives
Photonic Integration Approach
APACHE relies on the unique combination of high-speed indium phosphide (InP) monolithic elements, Silicon (Si) submounts and ultra low-loss silica-on-silicon planar lightwave circuits (PLC) for achieving characteristics such as cost-effectiveness, high yield, small footprint, device scaling and low power consumption. The APACHE integration approach foresees both horizontal and vertical integration scale increase through a “monolithic-on-hybrid” technology approach. Horizontal integration results in an increase of on-chip functionality exploiting hybrid integration planar lightwave circuit fabrication technology. Using this technique, low-loss passive assembly is achieved allowing for the integration of different photonic elements such as lasers, amplifiers, modulators and filters in a serial configuration using silicon submounts.
Objective 1: Development of advanced hybrid integration platform
Within APACHE, advanced silica-on-silicon hybrid integration technology will be developed, acting as the optical printed circuit board (or motherboard) providing the passive waveguide interconnection fabric. Precision cleaved, mode expanded monolithic components are passively assembled on a silicon submount (daughterboard) which is in turn passively assembled into the planar silica motherboard. The approach requires a unified design method for the hybrid device which, as well as defining the alignment features necessary for assembly, defines the mode sizes of the optical components at the interfaces between active and passive elements. Moreover, compared to InP, passive silica-based waveguides show lower absorption losses, lower group velocity dispersion, better matching to optical fibres and less temperature sensitivity.
Objective 2: Modelling and simulation tools development
Currently, there are no commercially available simulation tools for complex photonic integrated circuits involving non linear active and passive devices, and there are no design tools for hybrid or monolithic integrated circuits that incorporate the appropriate fabrication design rules. In the framework of the project, sophisticated 3D simulation tools will be designed and developed, enabling efficient modelling of large-scale photonic systems-on-chip. Presently, simulations of the physical behaviour of (hybrid) optical photonic circuits is limited by factors as computer capabilities, model inadequacies and accurate physical measurements of key parameters. With respect to computer limitations both main-memory and CPU-speed/count are key bottlenecks for full physical 3D simulations, therefore requiring model simplifications and approximations which results in a trade-off between accuracy and simulation time. Model limitations are therefore explicitly a requirement based upon current computer hardware. On the other hand, the existing knowledge for detailed physical effects in materials and the processes to create the structures is in many cases not complete, fact that leads to errors. Within APACHE a non linear active material model will be implemented based on simple S-matrix and/or Rate equations and validated with the actual performance of fabricated structures and devices. Furthermore the existing design tools will be extended with additional functionality to combine designs from the different material domains, supported by auto-routing and fabrication rules. This will include the actual manufacturing process tolerances and the influence of these on the actual performance.
Objective 3: Development of Arrays of WDM lasers
Within APACHE, monolithic integration technology will be developed to enable the efficient fabrication of continuous wave laser arrays, compatible with the APACHE hybrid PLCB platform. Two approaches will be used using DFB laser arrays and SOA gain blocks. The DFB arrays will be complex-coupled buried-heterostructure (BH) DFB lasers with integrated spot size converter (taper), for providing matching of the optical field of the laser chip to the silica waveguide on the PLC motherboard, in order to minimise the coupling losses. The two section devices will consist of an active DFB-section and a passive taper section. Efficient active-passive coupling with a coupling loss <0.5dB is achieved using the integrated twin-guide approach, i.e. passive and active sections use a common underlying waveguide. The spot size converter will be realised by tapering the width of the optical waveguide in the passive section towards the output facet. Complex-coupled gratings will be used in order to obtain a single mode yield close to 100% which is an essential pre-condition to realize DFB-laser arrays. In the other approach, monolithically integrated SOA arrays will be used as gain blocks coupled to wavelength selective passive optical components to generate a comb of discrete laser wavelengths. This approach is targeted at uncooled operation where the active devices do not need to be temperature controlled to achieve stable wavelength output.
Objective 4: Fabrication of InP Modulators for OOK/DPSK Signals
In contrast to the current approach for developing electro-optic modulators using lithium niobate technology, within APACHE, a unified “all-semiconductor” approach will be adopted for developing monolithic InP modulators. Advanced fabrication capabilities on InP can lead to modulator structures with 20-50 times smaller footptint, low switching voltages (~50% reduction) and enhanced biasing stability without the need for any electronic control loop. These monolithic chips will be designed so as to be compatible with the hybrid integration platform and allow for efficient and passive assembly onto new precision-machined silicon submounts. InP Mach-Zehnder modulators and EAMs developed will have high-speed travelling wave electrodes (TWE) and integrated spot size converters (tapers) for matching the optical field of the modulator chip to the silica waveguide on the optical printed circuit board (or motherboard), in order to minimise the coupling losses. To match the target of passive alignment a precision cleaving technology (with submicron accuracy) will be developed and implemented to meet the specifications of the APACHE integration platform.
Objective 5: Fabrication of nested InP Mach-Zehnder Modulator arrays
Having established the necessary methodology and technology for developing InP Mach-Zehnder modulator chips, monolithically-integrated nested-Mach-Zehnder structures will be also designed and fabricated in order to develop multi-level phase modulators, such as QPSK. The modulator structure will be customized in order to be capable of modulating either a single QPSK channel or two DPSK channels using the same fabricated InP structure, by nesting two Mach-Zehnder modulators and appropriately choosing the driving electronic modulating signals. Specialised silicon submounts will be developed in order to accommodate the monolithic chips and their corresponding passive high-precision micron-tolerance assembly on the APACHE hybrid platform.
Objective 6: High-Speed Receiver arrays
APACHE will address the issues related to the optoelectronic conversion of high bandwidth signals at the receiver end. In more detail, within the project, the scaling advantages of “monolithic-on-hybrid” technology proposed will be exploited to develop arrays of high bandwidth photodiodes (>100 GHz) into a single photonic integrated circuit. The integration of the photodiodes under the same planar lightwave circuit, with all DC and RF fan-outs in a single package will provide 50-80% cost reduction and enable more cost-effective receiver subsystems for multi-level modulation formats or high-speed and capacity WDM systems.
Objective 7: Multi-Functional Optical Regenerators
Within APACHE, optical regenerators will be developed, capable of processing multiple modulation format signals at bit-rates exceeding 100 Gb/s. The versatility of the planar lightwave circuit and the corresponding advanced pigtailing capabilities will be exploited for fabricating high-complexity waveguides in order to allow for selectable regeneration of OOK/DPSK/DQPSK signals according to signal propagation within the photonic chip. Up to eight parallel SOAs flip-chipped on precision-machined silicon submounts will be passively assembled on the motherboard, unlocking the full potentials for photonic processing systems-on-chip.